Unless otherwise indicated herein, the materials described herein are not prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.
Parasitic resistance (e.g., equivalent series resistance (ESR)) and parasitic inductance (e.g., equivalent series inductance (ESL)) of capacitors are detrimental to high frequency performance of integrated circuits (ICs). Capacitance of a parallel plate capacitor may depend on an area that the capacitor occupies in a printed circuit board (PCB). However, space in the PCB may be a scarce resource since numerous circuit components may be integrated into the PCB. The parallel plate capacitor may usually appear on another side of the PCB connected with vias and/or traces that may incur extra inductance (e.g., ESL) and resistance (e.g., ESR) and that may lower a resonance frequency of the capacitor.
A ball grid array (BGA) IC may have dense packaging limitations for decoupling capacitors and other passive IC components. Even in outer row pads, providing bias to power traces in a BGA IC may be difficult with pitches that are less than or equal to 0.5 millimeter. In high frequency applications (e.g., 25 GHz or beyond), effective decoupling at BGA pads may be needed, e.g., using capacitors. However, decoupling at microwave and terahertz frequencies may be difficult due to parasitic resistance, parasitic inductance, and time to charge and/or discharge the capacitors.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.